1. Field of the Invention
The present invention relates generally to semiconductor integrated circuits, semiconductor integrated circuit design support devices, and semiconductor integrated circuit manufacturing methods and, in particular, to a semiconductor integrated circuit having a design for testability, a semiconductor integrated circuit design support device, and a semiconductor integrated circuit manufacturing method.
2. Description of the Related Art
Semiconductor integrated circuits are generally provided with scan cells for conducting a scan test. Taking, for example, in MUX (multiplex) scan cells, a multiplexer is inserted so that a data input of a normal flip-flop is switched to a scan input using a scan enable signal as one of the selectable signals. Then, the areas of the scan cells become large, resulting in set-up timing being messed up.
As scan path designs, there are a full scan design and a partial scan design. The full scan design is a design in which all or most of the flip-flops of target sequence circuits are made into scan cells and a shift register configuration is structured in the scan cells. The partial scan design is a design in which some flip-flops of target sequence circuits are made into scan cells and the shift register configuration is structured in the scan cells.
Generally, the full scan design is more excellent than the partial scan design in controllability and observability relative to a circuit as well as in failure detection rate by a scan/ATPG test.
Recently, with scaling-up and high integration of semiconductor integrated circuits and an improvement in operating frequency, problems have emerged such as increased chip area, increased power consumption, degraded timing convergence, and degraded wiring convergence of layouts, which are caused by the scan designs. Conventionally, in order to cope with these problems, the scan rate is lowered by using the partial scan design to prevent an increase in chip area, degraded timing, and degraded wiring convergence. However, taking such a measure will disadvantageously sacrifice a high failure detection rate.
Note that Patent Document 1 discloses a scan test method for semiconductor integrated circuits of high integration and a semiconductor integrated circuit tested by the scan test method.
Patent Document 1: JP-A-2004-233084